1. Field of the Invention
The present invention relates to an analog to digital converter (hereinafter referred to as A-D converter) which converts an analog signal into a digital signal, and more particularly, to a series-parallel type A-D converter for realizing high speed operation and low power consumption.
2. Description of the Background Art
AD converters have come to be utilized in various kinds of apparatus as more and more signals come to be processed in digital manner, and thus, there exists the need for an A-D converter enabling high speed operation, high accuracy and low power consumption. As to A-D converters for video cassette recorders (VCRs), for example, an A-D converter having an accuracy in the order of ten bits is required, since high definition TVs, VCRs or the like have been developed. A serial-parallel type A-D converter realizing above-mentioned high speed operation and low power consumption is disclosed in Journal of Electronics, Information and Communication Engineers of Japan, C-II, Vol. J7, 4-C-II, No. 2, pp. 81-91, February 1991. A conventional A-D converter having the same structure as the above-described A-D converter will be described below referring to the drawings.
FIG. 8 shows a structure of a conventional A-D converter.
In FIG. 8, an A-D converter includes a sample and hold circuit 1, an upper comparator group 2, a clock generator 6, an upper encoder 7, a lower ladder resistance network 9, a lower comparator group 10, a lower encoder 11, an adding/subtracting circuit 13, an upper ladder resistance network 20, an analog switch group 21, and a buffer amplifier group 22.
Sample and hold circuit 1 is provided for sampling an instantaneous value of an applied analog signal, holding the same for a certain period of time, and outputting the same to upper comparator group 2 and buffer amplifier group 22.
Upper ladder resistance network 20 is formed by a plurality of resistors which are connected in series. Predetermined potentials VRT and VRB are respectively input to both ends of upper ladder resistance network 20. Upper ladder resistance network 20 divides the voltage between VRT and VRB by the resistors into predetermined values which are output to upper comparator group 2 as upper reference potentials. Upper ladder resistance network 20 generates and outputs intermediate reference potentials, which are intermediate potentials of upper reference potentials, to analog switch group 21.
Upper comparator group 2 is formed by a plurality of comparators, each of which compares an output signal of sample and hold circuit 1 with an upper reference potential in response to a clock signal output from clock generator 6. For example, each comparator outputs a signal of a "H" (high potential) level when the input signal is larger than the reference potential, while it outputs a signal of a "L" (ground potential) level when the input signal is smaller than the reference potential. The output signal is called a thermometer code. Upper comparator group 2 detects a border between the "H" level and the "L" level of the thermometer code. In other words, according to logical determination of the result of each comparison, only one comparator corresponding to the border of the thermometer code is rendered operative (hereinafter referred to as activation). All comparators included in upper comparator group 2 are connected to analog switch group 21. One comparator which is activated outputs a control signal such as the "H" level signal to analog switch group 21 for controlling analog switch group 21. Other comparators output, for example, the "L" level signals to analog switch group 21 as control signals. Those control signals are output to upper encoder 7 as upper comparison result signals.
Upper encoder 7 is connected to adding/subtracting circuit 13. Upper encoder 7 converts the applied upper comparison result signals into an upper digital data by a predetermined logical processing and outputs the data to adding/subtracting circuit 13.
Analog switch group 21 includes analog switches the number of which is three times the number of comparators included in upper comparator group 2, and is connected to buffer amplifier group 22. Analog switch group 21 turns on three analog switches connected to one comparator which has been activated in response to control signals output from upper comparator group 2. The three analog switches output to buffer amplifier group 22 two intermediate reference potentials which are directly above and below the upper reference potential applied to the activated comparator.
Buffer amplifier group 22 includes four buffer amplifiers and is connected to lower ladder resistance network 9 and to lower comparator group 10. The output signal from sample and hold circuit 1 is input to one buffer amplifier included in buffer amplifier group 22, and the output signal therefrom is provided to lower comparator group 10. Three intermediate reference potentials output from analog switch group 21 are applied to the other three buffer amplifiers and then output to lower ladder resistance network 9.
Lower ladder resistance network 9 is formed by a plurality of resistors which are connected in series. The highest potential and the lowest potential among intermediate reference potentials output from buffer amplifier group 22 are input to both ends of lower ladder resistance network 9, while the middle one of the intermediate reference potentials is input to an middle point. Lower ladder resistance network 9 divides the voltage among those intermediate reference potentials by a plurality of resistors for outputting a plurality of lower reference potentials to lower comparator group 10.
Lower comparator group 10 is formed by a plurality of comparators, each of which is connected to lower encoder 11. Lower comparator group 10 operates similarly to upper comparator group 2. In other words, it compares the output signal of sample and hold circuit 1 applied via the buffer amplifier with lower reference potentials output from lower ladder resistance network 9 in response to a predetermined clock signal (not shown), and then outputs lower comparison result signals to lower encoder 11.
Lower encoder 11 is connected to adding/subtracting circuit 13. Lower encoder 11 encodes the applied lower comparison result signals by a predetermined logical processing and outputs a lower digital data to adding/subtracting circuit 13.
Adding/subtracting circuit 13 carries out addition/subtraction of upper and lower digital data which are applied from upper encoder 7 and lower encoder 11, respectively, and outputs a digital signal corresponding to the applied analog signal.
Operation of the A-D converter having the above-described structure will be described. The applied analog signal is sampled and held in sample and hold circuit 1 and is output to upper comparator group 2. A plurality of upper reference potentials which are resistance-divided in upper ladder resistance network 20 are output to upper comparator group 2.
Upper comparator group 2 compares the output signal from sample and hold circuit 1 with upper reference potentials in response to the clock signal output from clock generator 6 and outputs upper comparison result signals to upper encoder 7. Upper encoder 7 encodes the upper comparison result signals by a predetermined logical processing and outputs an upper digital data to adding/subtracting circuit 13. The upper digital data of the applied analog signal is thus generated.
Upper comparator group 2 detects a boarder between the "H" level and the "L" level of a thermometer code according to the upper comparison results, and activates only one comparator which corresponds to the boarder. The activated comparator outputs to analog switch group 21 a control signal for turning on analog switches. Analog switch group 21 turns on three analog switches in response to the applied control signal, and outputs three intermediate reference potentials to buffer amplifier group 22. Buffer amplifier group 22 outputs the applied three intermediate reference potentials to lower ladder resistance network 9. Those three intermediate reference potentials serve as reference potentials for lower comparison. The voltage between the highest potential and the lowest potential among intermediate reference potentials is equivalent to 2LSBs (Least Significant 2 Bits) of the upper comparison, and the potential between the highest potential and the middle potential is equivalent to 1LSB thereof. The voltage equivalent to 2LSBs in the upper comparison is divided into two or more for lower comparison of the analog signal. In addition to the highest potential and the lowest potential, the middle potential is input to lower ladder resistance network 9 in order to reduce the influence of stray capacitance over the settling time.
Lower ladder resistance network 9 by provides plurality of lower reference potentials to lower comparison group 10 by resistive-division of input intermediate potentials. Lower comparison group 10 compares the output signal from sample and hold circuit 1, which is applied through the buffer amplifier, with lower reference potentials and outputs the lower comparison result signals to lower encoder 11. Lower encoder 11 encodes the applied lower comparison result signals by a predetermined logical processing and outputs a lower digital data to adding/subtracting circuit 13. The lower digital data of the applied analog signal is thus produced.
Adding/subtracting circuit 13 digitally corrects the applied upper and lower digital data by adding/subtracting and finally produces a digital signal corresponding to the applied analog signal for output. Accordingly, the applied analog signal is converted into the digital signal for output.
As a more specific example, a 10-bit series-parallel type A-D converter having a structure similar to the above-described conventional A-D converter will be described referring to the drawings. FIG. 9 shows the structure of a conventional 10-bit A-D converter. The A-D converter shown in FIG. 9 is a series-parallel A-D converter including the upper part corresponding to 5 bits and the lower part corresponding to 6 bits enabling conversion of 10 bits.
In FIG. 9, the A-D converter includes sample and hold circuit 1, upper comparator group 2, clock generator 6, upper encoder 7, lower ladder resistance network 9, lower comparator group 10, lower encoder 11, adding/subtracting circuit 13, upper ladder resistance network 20, analog switch group 21, and buffer amplifier group 22. Same numerals are given to portions corresponding to those in the A-D converter shown in FIG. 6 since connections and the like are the same, and thus the description thereof will not be repeated.
Upper ladder resistance network 20 includes resistors R0-R65. Upper comparator group 2 includes comparators CH0-CH31. The resistance value of resistors R0-R65 is set to r/2. Normally, 2.sup.5 +1=33 resistors are used in order to carry out the upper comparison of 5 bits. However, those resistors are further divided into two so that 66 resistors in total are used in this case in order to output the intermediate potentials of the intermediate reference potentials to lower ladder resistance network 9 in addition to the highest and the lowest potentials of the intermediate reference potentials. The comparison of upper 5 bits can be carried out by the above-mentioned structure.
Analog switch group 21 includes analog switches S0-S95. Three analog switches are connected to each comparator included in the upper comparator group 2. Those three analog switches respectively output three intermediate reference potentials including the highest, the middle, and the lowest potentials corresponding to the activated comparator to lower ladder resistance network 9 via buffer amplifier group 22.
Lower ladder resistance network 9 includes resistors RL0-RL64. Lower comparator group 10 includes comparators CL0-CL63. The above-mentioned structure enables the comparison of lower 6 bits.
An operation of the A-D converter structured as above will be described in detail. Assume that comparator CH30 included in upper comparator group 2 is activated as a result of the upper comparison. The activated comparator CH30 outputs a control signal to analog switches S87, S91, and S94 for turning on the analog switches. In response to the applied control signal, analog switches S87, S91, and S94 are turned on. Accordingly, analog switch S94 outputs an intermediate reference potential VT to a buffer amplifier B2 in buffer amplifier group 22, analog switch S91 outputs an intermediate reference potential VM to a buffer amplifier B1, and analog switch S87 outputs an intermediate reference potential VB to a buffer amplifier B0. Buffer amplifiers B0-B2 output the applied intermediate reference potentials VB, VM, and VT respectively to lower ladder resistance network 9.
Lower ladder resistance network 9 divides the voltage between intermediate reference potentials VT and VB by resistors RL0-RL64 and outputs 64 lower reference potentials to lower comparator group 10. Comparators CL0-CL63 included in lower comparator group 10 respectively compares the output signal of sample and hold circuit 1 applied via buffer V3 with the lower reference potentials. Since comparator CH30 has been activated as a result of the upper comparison, the output signal of sample and hold circuit 1 is between upper reference potentials VH and VL. Accordingly, when intermediate reference potentials VT and VB are used as the lower reference potentials, the output signal from sample and hold circuit 1 inevitably exists therebetween. This enables lower comparison of the analog signal applied to sample and hold circuit 1. Lower comparator group 10 outputs lower comparison result signals to lower encoder 11. Lower encoder 11 encodes the applied 64 comparison result signals and outputs a lower digital data to adding/subtracting circuit 13. Adding/subtracting circuit 13 corrects the applied lower and upper digital data and outputs a 10-bit digital data.
Now, a conventional A-D converter using a differential amplifier will be described below. The power supply voltage of A-D converters tends to be reduced in response to the need for low power consumption of the commercially available electronic devices in which the A-D converter is used. Thus, A-D converters having an increased dynamic range and a high resistance against noises or the like in which complementary differential analog signals are input instead of a single analog signal have been developed. Such an A-D converter is disclosed, for example, in "A 10-bit 75-MSPS Subranging A-D Converter with Integrated Sample and Hold", IEEE JSSC, vol. 25, No. 6, Dec., 1990. The conventional A-D converter having the same structure as the above-described A-D converter will be described with reference to the drawings. FIG. 20 shows another structure of the conventional A-D converter.
Referring to FIG. 20, an A-D converter includes a sample and hold circuit 101, an upper A-D converting unit 102, a lower A-D converting unit 103, reference voltage controlling circuits 104, 107, a digital-to-analog converter (referred to as DAC hereinafter) 105, an analog subtracting circuit 106, and a differential amplifier 108. Upper A-D converting unit 102 includes an upper ladder resistance network 110, an upper comparator CU, a latch circuit LU, and an upper encoder 111. Lower A-D converting unit 103 includes a lower ladder resistance network 112, a lower comparator CL, and a lower encoder 113.
Sample and hold circuit 101 responds to a predetermined clock signal CK0 for sampling/holding a positive differential analog input signal AP and a negative differential analog input signal AN, respectively, and outputting those signals to upper ladder resistance network 110 and analog subtracting circuit 106. Differential reference voltages Vr are applied to reference voltage controlling circuit 104 and DAC 105. Reference voltage controlling circuit 104 is provided to set an input range of upper A-D converting unit 102 in response to differential reference voltages Vr. DAC 105 is provided to set an LSB step which is the minimum unit of the D-A conversion in response to differential reference voltages Vr. Reference voltage controlling circuit 107 is provided to set an input range of lower A-D converting unit 103 in response to differential reference voltages output from DAC 105.
Differential analog signals output from sample and hold circuit 101 are compared with a plurality of upper reference potentials by upper ladder resistance network 110 and a plurality of upper comparators CU, and upper comparison result signals are output to a plurality of latch circuits LU and DAC 105. The plurality of latch circuits LU are provided to latch the applied upper comparison result signals and output those signals to upper encoder 111 which outputs upper digital signals DU in response to the applied upper comparison result signals.
DAC 105 responds to the applied upper comparison result signals to output reference signals for subtraction to analog subtracting circuit 106. Analog subtracting circuit 106 subtracts those reference signals applied from DAC 105 from respective differential analog signals AP, AN applied from sample and hold circuit 101, and outputs differential analog signals for lower comparison to differential amplifier 108. Differential amplifier 108 amplifies those analog signals by a predetermined gain for output to lower ladder resistance network 112.
Lower ladder resistance network 112 and a plurality of lower comparators CL compare the applied differential analog signals for lower comparison with predetermined lower reference potentials and output comparison results to lower encoder 113. Lower encoder 113 outputs lower digital signals DL in response to those result signals.
By the above operation, differential analog signals AP, AN are converted into upper digital signals DU by upper A-D converting unit 102, and then, into lower digital signals DL by lower A-D converting unit 103.
Now, the subtracting operation conducted by the analog subtracting circuit shown in FIG. 20 will be described. FIG. 21(a) and 21(b) show subtraction results by the analog subtracting circuit shown in FIG. 20.
With reference to FIGS. 21(a) and 21(b), when triangular waves, for example, are input as positive and negative analog input signals AP, AN, DAC 105 responds to upper comparison result signals to output positive and negative D-A conversion result signals in a stepwise manner to analog subtracting circuit 106. In analog subtracting circuit 106, a positive D-A conversion result signal is subtracted from positive analog input signal AP, and similarly, a negative D-A conversion result signal is subtracted from negative analog signal AN. As a result, analog subtracting circuit 106 outputs triangular waves within a range corresponding to 1LSB as positive and negative subtraction result signals, respectively, to differential amplifier 108. More particularly, the positive subtraction result signal within the range of 1LSB is output into the positive domain, about the reference potential while the negative subtraction result signal within the range of 1LSB is output into the negative domain.
Next, the detailed description will be given about differential amplifier 108 which differentially amplifies the above-described positive and negative subtraction result signals. FIG. 22 is a circuit diagram showing a structure of the differential amplifier shown in FIG. 20.
With reference to FIG. 22, the differential amplifier includes resistances R101-R104, and transistors Q101, Q102. Resistance R101 is connected to power supply voltage V.sub.cc and transistor Q101. Transistor Q101 is connected to resistance R103. The positive subtraction result signal is input as an input voltage Vin1 to a base of transistor Q101. Resistance R103 is connected to a constant current source IS1 which is connected to the ground. Resistance R102 is connected to power supply voltage V.sub.cc and transistor Q102 which is connected to resistance R104. The negative subtraction result signal is input as a differential input voltage Vin2 to a base of transistor Q102. Resistance R104 is connected to constant current source IS1. An output voltage Vo1 is applied from a node between resistance R101 and transistor Q101. An output voltage Vo2 is applied from a node between resistance R102 and transistor Q102.
Input/output characteristics of the differential amplifier structured as above will be described. FIG. 23 is a graph showing a relationship between the differential input voltage and the collector current of the differential amplifier shown in FIG. 20. FIG. 24 is a graph showing a relationship between the differential input voltage and the output voltage of the differential amplifier shown in FIG. 20.
As shown in FIGS. 23 and 24, collector current Ic1, Ic2 and output voltage Vo1, Vo2 change exponentially, and a linear area in which the change is almost linear is limited to a region indicated by LR. The characteristic of the change in the exponential manner can be clearly seen in the region other than linear area LR, so that differential input voltage Vin1-Vin2 is not proportional to output voltage Vo1, Vo2, thus incurring an error during amplification.
The results of amplification of positive and negative subtraction result signals by the above-described differential amplifying circuit will be described below. FIGS. 25(a) and 25(b) are graphs showing input/output characteristics of the differential amplifier shown in FIG. 20.
With reference to FIG. 23, if the positive or negative subtraction result signal in the shape of triangular wave is input about the reference potential positive and negative output signals are supplied respectively into the positive and the negative domain. More particularly, the range (2LSB) of the positive and negative subtraction result signals serving as input signals is larger than the range of linear area LR of the differential amplifier. In the region other than linear area LR, thus, the output signal is not proportional to the input signal, so that a portion NLR is generated in which a highly accurate amplification cannot be conducted. In the input/output voltage characteristics of the differential amplifier, linear area LR becomes larger if a load resistance on an emitter side is increased. On the contrary, a voltage gain is reduced by the increased input range. The input range thus should be made larger in order to obtain the same output, which contradicts an end of reducing the voltage. Therefore, in order to achieve the reduction of the voltage, the differential amplifier has been used within the above-described range, with sacrificing an accuracy during amplification to a certain extent.
In the conventional A-D converter structured as above, the intermediate reference potentials of upper ladder resistance network 20 are transmitted through analog switch group 21 and buffer amplifier group 22 to lower ladder resistance network 9. At this time, upper comparator group 2 carries out upper comparison in response to the clock signal output from clock generator 6. Intermediate reference potentials of upper ladder resistance network 20 change according to the potential level of the analog signal applied via sample and hold circuit 1. Thus, the lower reference potentials of lower ladder resistance network 9 changes at every clock period. Accordingly, ringing is generated, because the stray capacitance of lower ladder resistance network 9 is charged/discharged according to the change of the lower reference potentials. Since the ringing affects the settling time of the lower reference potentials, the operating frequency of the A-D converter cannot be increased.
If the operating frequency is to be increased without changing the above-described structure, restraint of the ringing is required. In order to restrain the ringing, a large amount of current sufficient to charge/discharge the stray capacitance of the lower ladder resistance network 9 in a short time and also to reach a stable point is required, which causes increase of the power consumption of the device.
Further, in the conventional A-D converter using the differential amplifier, the highly accurate amplification of the lower analog signals cannot be conducted, since the positive and negative subtraction result signals are input respectively into the positive and negative domains about the reference potential. Accordingly, the lower A-D converting operation should be carried out using the lower analog signals having errors. As a result, the lower output signals include errors, and the highly accurate A-D conversion cannot be carried out.